VHDL-2008 for Synthesis

Course Objectives

This course introduces the new and changed features of VHDL-2008, in order to improve and enhance hardware engineer´s skills.
The course goes into great depth and teaches the advanced features of the VHDL-2008 language through code examples, shows how they improve the language as a tool for design and verification, and guides how to employ them in new designs.
The training covers the synthesized new structures, operators, and highlight the hardware result, using the Quartus Prime Pro.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory.This course also enriches digital engineers with many years of experience.

General Information


FPGA design

Duration & Attendance

Live Training on May 4-7

Target Audience

Hardware engineers who develop FPGAs and would like to enhance their skills, in order to become experts with VHDL-2008 new language features for design and verification

Additional Information

Teaching Methods & Tools

Simulator: Modelsim
Synthesizer and Place & Route: Quartus Prime Pro