Partial Reconfiguration with Altera FPGAs

Course Objectives

This course provides all necessary theoretical and practical know-how to use the partial reconfiguration methodology and design flow in Altera FPGAs, in order to reprogram one or more parts of a design dynamically, while the rest of the design continues to operate.  

The course begins with an overview of what is partial reconfiguration, its main applications, PR definitions for region, partition, persona, PR host and control block.
The course continues with PR hierarchical design flow, design partition recommendations, tools and LogicLock regions. Then timing closure is discussed for PR, changing port values during PR, management of global resources, debugging PR regions.
The course teaches how to design PR host (internal or external), PR host IP for region management, PR controller IP, how to program and configure PR, and PR project full design flow in greater details. 

The course includes extensive hands-on labs.
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General Information

Prerequisites

1. FPGA design experience
2. VHDL/SystemVerilog
3. Quartus Prime Pro
4. TimeQuest
5. Avalon bus
6. ModelSim/Questa

Duration & Attendance

2 days

Target Audience

Hardware engineers who develop with Altera FPGAs (Arria 10/Stratix10/Agilex) and would like to apply the PR methodology into their design.

Additional Information

Teaching Methods & Tools

1. Quartus Prime Pro
2. Course book
3. Lab's handbook and lab files
4. Altera Stratix 10 GX FPGA Development Kit (optional)

Evaluation & Certification

Each attendee receives an official certificate from Altera and from Arm (Exam must be passed).