Introduction to Nios V Processors

Course Objectives

This course provides all theoretical and practical know-how to create and manage software projects for Nios V processors.  
The course starts by reviewing the Nios V processor variants as well as the architectures difference.
Then, you learn how to integrate Nios V to Quartus project using the hardware design flow in the Platform Designer tool and generate the files for software developer.
The course continuous by going through the software development flow including BSP editor, HAL, linker script, timers, interrupt and exception handling, etc.
The Ashling RiscFree IDE for Altera FPGAs is also covered and used in the hands-on labs.
The course ends by discuss the various booting and configuration options and how to debug Nios V processors.

General Information

Prerequisites

· Embedded system software design
· C/C++ programming

Duration & Attendance

2 days

Target Audience

Hardware and Software engineers who would like to integrate Nios V into their project.

Additional Information

Teaching Methods & Tools

1. Course book
2. Lab's handbook and lab files
3. Stratix 10 GX FPGA development kit
4. Quartus Prime Software Pro Edition v25.3 with Ashling RiscFree IDE for Altera FPGAs, license for Nios V/g and Nios V/m processors.
5. Stratix 10 Development Kit device support installed

Evaluation & Certification

Each attendee receives an official certificate from Altera (Exam must be passed)