Designing with Quartus Prime Pro

This 3-days training provides all necessary information to start designing with Altera FPGAs using Quartus Prime Pro software.

The course starts with an overview of the Quartus Prime design software features, Quartus Prime projects types and management, design methodology, and using IP cores from the IP catalogue.
Various system design entry tools such as Platform system integration tool, state machine editor, memory editor, oneAPI SYCL HLS, Altera FPGA AI Suite, and DSP Builder are also introduced in high level. 

The course continues with the Quartus Prime compilation flow, working with messages, viewing compilation reports, RTL and technology views, state machine viewer, and how to use the chip planner tool.
The course also touches upon simulation, synthesis and Place & Route settings as well as, assignment editor, optimizations, design assistant and scripting methods to automate design tasks.

Next, the I/O planning with the pin planner & Interface Planner tool is introduced and how to use it efficiently in complex designs.

The training continuous by introducing Platform Designer, incremental optimization, and block-based design methodologies.
Then Timing Analyzer tool introduced to enable writing SDC files and analyze timing.

The course ends with tips how to convert design from non-Altera to Altera FPGA.
The course includes extensive practical work. The practical labs cover all of the theory.