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Designing with Agilex 5 SoC
Course Objectives
This 4-days course provides all
necessary know-how for hardware engineers that would like to design with Agilex
5 SoC FPGA.
The training adds a rich set of hands-on labs to provide the attendee to experience with the device either on EVB or just with FPGA design software.
Altera Agilex 5 Family provides midrange FPGAs offering world-class features and capabilities that address design challenges across various markets.
The training starts by introducing the Agilex 5 FPGAs architecture (I/O, DSP, RAM, PLLs, etc.), it´s 2nd generation Hyperflex architecture, and the Quartus Prime Pro design software for Agilex 5.
The training continues by teaching how to implement high-speed external memory interfaces, high speed serial interfaces, PCIe and Ethernet (with TSN).
Next, the Hard Processor Subsystem (HPS) is covered with Cortex-A76 and Cortex-A55, along with their peripherals, NoC architecture, design considerations and debug capabilities.
The training ends with the Agilex 5 security features and functional safety. An optional extension available is the FPGA AI suite for Agilex 5 and the design flow for AI.
The training adds a rich set of hands-on labs to provide the attendee to experience with the device either on EVB or just with FPGA design software.
Altera Agilex 5 Family provides midrange FPGAs offering world-class features and capabilities that address design challenges across various markets.
The training starts by introducing the Agilex 5 FPGAs architecture (I/O, DSP, RAM, PLLs, etc.), it´s 2nd generation Hyperflex architecture, and the Quartus Prime Pro design software for Agilex 5.
The training continues by teaching how to implement high-speed external memory interfaces, high speed serial interfaces, PCIe and Ethernet (with TSN).
Next, the Hard Processor Subsystem (HPS) is covered with Cortex-A76 and Cortex-A55, along with their peripherals, NoC architecture, design considerations and debug capabilities.
The training ends with the Agilex 5 security features and functional safety. An optional extension available is the FPGA AI suite for Agilex 5 and the design flow for AI.
General Information
Prerequisites
1.
VHDL/Verilog
language
2. FPGA design experience of at least 3 years
3. Experience with SoC FPGA design
2. FPGA design experience of at least 3 years
3. Experience with SoC FPGA design
Duration & Attendance
4 days (+1 optional)
Target Audience
FPGA engineers who would like to design with Agilex 5 SoC FPGA family
Additional Information
Teaching Methods & Tools
1.
Course
book
2. Lab handbook
3. Trainer solutions to all labs
2. Lab handbook
3. Trainer solutions to all labs