Designing with Agilex 5 SoC

This 5-days deep training provides all the necessary know-how for hardware engineers that would like to design with the Altera Agilex 3 SoC family.

The training provides extensive hands-on labs to experience with the various features. 

The training starts by introducing the Agilex 5 family and its architecture.
Then the Hyperflex architecture and how to use it efficiently is discussed in details.
The Quartus Prime Pro advanced features that support Agilex 5 are introduced along with practical hands-on labs. 

In the second day the training continuous with the high-speed memory interfaces, high speed serial interfaces (GTS transceivers and various IPs), and the MIPI interface with CSI2/DSI2. 

In the third day the Hardware Processor System (HPS) is introduced along with its peripherals, interfaces, Network on Chip (NoC), and Cortex-A76 & Cortex-A55 architecture and capabilities.
This part covers also the boot flow in details, and how to generate the first and second bootloaders (FSBL, SSBL). 

In the fourth day the Agilex 5 configuration schemes are discussed in details including the Remote System Update (RSU) design flow.
In addition, the Agilex 5 security features are discussed in details including the Secure Device Manager (SDM) and the secure boot flow. 

In the fifth day the Agilex 5 DSP with Tensor block architecture is introduced.
Then the deployment of AI IP design flow is discussed in details.