Building Interfaces with Arria 10 High-Speed Transceivers

Course Objectives

In this course, you will learn how you can build high-speed, gigabit interfaces using the 20-nm embedded transceivers found in Arria 10.
You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols.
You will learn how to optimize and debug both the digital and analog sections of your transceiver design.
You will gain an understanding of the transceiver reconfiguration controller and how you can use it to fine tune transceiver settings and add flexibility to your transceiver design.
Lastly, you will be made aware of common "gotchas” that occur in transceiver designs and what steps you can take to avoid them.
The course contains hands-on labs to experience with Arria 10 transceiver IP cores configuration, simulation, using the transceiver Toolkit (optional), and enabling Arria 10 transceiver reconfiguration in the Native PHY IP core.

General Information


FPGA design
Quartus and TimeQuest
SignalTap II
Note: familiarity with high-speed interfaces and transmission protocols is helpful, nut not required

Duration & Attendance

2 days

Target Audience

Hardware engineers who develop with Arria 10 and would like to build gigabit interfaces

Additional Information

Teaching Methods & Tools

  • Synthesizer and Place & Route: Quartus Prime
  • Course book (including labs)
  • Stratix V or Arria 10 Evaluation board (optional)