Achieving Timing Closure in Altera FPGAs

This course provides all necessary theoretical and practical know-how to analyze and fix timing failures for variety use cases in Altera FPGAs.
The course goes into great depth and touches upon every aspect of timing failures due to setup and hold negative slack, I/O input/output delays, reset issues, CDC, high fanout, global clock networks, over constrained design, as well as timing exceptions. 
The course begins with methodology for timing closure, the FPGA architecture, and the effect of incorrect timing constraints, and HDL coding considerations. 
The course continuous by reviewing the various analysis tools in the Quartus Prime Pro software, such as Design Assistant, Fitter reports, Snapshot Viewer, Chip Planner and Design Metrices reports. 
The course continues with an in depth solutions for various timing failures use cases such as CDC congestion, too many logic levels, high fanout, conflicting SDC assignments, conflicting location assignments, tight timing requirements, clock crossing, and clock skew. 
The course includes extensive practical work. The practical labs cover all the theory.