Advanced Verilog for High Productivity

After a great success at Apple and Samsung, the "Advanced Verilog for High Productivity" training is now available to the open market.
Experience with greatest and latest techniques to decrease dynamic power consumption by decreasing the bus toggling rate, clock and alternative coding for FSM and signals. 
Learn how to decrease circuit area by outperform the synthesizer with precise RTL coding using functionality and resource sharing approach.
Experience an alternative approach to pipeline in order to speed up arithmetic circuits (counters, adders, multipliers, dividers, floating point and comparators).

For detailed syllabus:

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