Timing Analysis with TimeQuest
Course Objectives
This course provides all
theoretical and practical know-how start writing sdc files and analyze your
design in TimeQuest tool.
The training starts with an overview of what need to be constrained in every design, the timing terminology used by the tools.
The training continuous by introducing the clock constraints, I/O constraints and exception constraints.
The training explains how to generate and read the various reports in TimeQuest in order to solve timing issues.
The course includes extensive practical work. The practical labs cover all the theory.
The training starts with an overview of what need to be constrained in every design, the timing terminology used by the tools.
The training continuous by introducing the clock constraints, I/O constraints and exception constraints.
The training explains how to generate and read the various reports in TimeQuest in order to solve timing issues.
The course includes extensive practical work. The practical labs cover all the theory.
General Information
Prerequisites
1. FPGA
design
2. FPGA architecture
3. Quartus Prime Pro software
2. FPGA architecture
3. Quartus Prime Pro software
Duration & Attendance
2 days
Target Audience
Digital hardware engineers who program with VHDL/Verilog languages and would like to constrain and analyze their design timing.
Additional Information
Teaching Methods & Tools
1. Quartus
Prime Pro
2. Course book
3. Lab handbook and project files
2. Course book
3. Lab handbook and project files
Evaluation & Certification
Each attendee receives an official
certificate from Altera (Exam must be
passed)