Designing with i.MX6 Architecture
Course Objectives
Designing with i.MX6 architecture is a 3 days NXP official course.
The course goes into great depth and provides all necessary know-how to develop software for systems based on i.MX6 processor.
The first day starts by overviewing the i.MX6x Family and its Target applications, Device architecture (QuadPlus/Quad/DualPlus/Dual/Dual-Lite/Solo/Solo-Lite/SoloX/SLL/UltraLite/ULL/ULZ), and family roadmap.
The course continuous with deep dive training of all i.MX6 internal blocks and accelerators such as memory system and DDR controller (MMDC), USB, SATA, PCI-E, eMMC/SD, NAND controller, Audio subsystem, clocking and reset, and power management unit.
The second day covers the Cortex-A9 MPCore architecture and capabilities, the smart DMA (SDMA), I/O muxing (with IOMUX tool), and GPMI and NAND interface subsystem, 1G Ethernet + IEEE1588, and MIPI display and sensor interface.
The third day covers the boot process (including secured boot with HAB) and boot devices, security features and hardware blocks, Image Processing Unit (IPU), Video Processing Unit (VPU), Graphics Processing Unit (GPU), and HDMI.
The course goes into great depth and provides all necessary know-how to develop software for systems based on i.MX6 processor.
The first day starts by overviewing the i.MX6x Family and its Target applications, Device architecture (QuadPlus/Quad/DualPlus/Dual/Dual-Lite/Solo/Solo-Lite/SoloX/SLL/UltraLite/ULL/ULZ), and family roadmap.
The course continuous with deep dive training of all i.MX6 internal blocks and accelerators such as memory system and DDR controller (MMDC), USB, SATA, PCI-E, eMMC/SD, NAND controller, Audio subsystem, clocking and reset, and power management unit.
The second day covers the Cortex-A9 MPCore architecture and capabilities, the smart DMA (SDMA), I/O muxing (with IOMUX tool), and GPMI and NAND interface subsystem, 1G Ethernet + IEEE1588, and MIPI display and sensor interface.
The third day covers the boot process (including secured boot with HAB) and boot devices, security features and hardware blocks, Image Processing Unit (IPU), Video Processing Unit (VPU), Graphics Processing Unit (GPU), and HDMI.
General Information
Prerequisites
- Computer architecture background
- ARM Cortex-A is an advantage but not mandatory
- Experience in developing embedded systems
Duration & Attendance
3 day
Target Audience
Software engineers that would like developing software and BSP for platforms based on i.MX6 SoC
Additional Information
Teaching Methods & Tools
- NXP official course book