Designing with DSP Builder for Altera FPGAs

Course Objectives

Learn the timing-driven Simulink® design flow to implement high-speed DSP designs. 
This course focuses on implementing DSP algorithms using the advanced blockset capability of DSP Builder — an interface between Quartus Prime software & MATLAB and Simulink from MathWorks.
You´ll analyze & design your DSP algorithm using the DSP Builder advanced blockset in MATLAB & Simulink.
You´ll explore architecture & performance tradeoffs with system-level constraints.
Also you´ll verify functionality & performance of generated hardware in the Quartus Prime software.
Finally, you´ll speed design time by incorporating ready-made ModelIP cores in your design.

The course includes extensive hands-on labs.
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General Information

Prerequisites

  • Familiarity with DSP fundamentals and design 
  • Familiarity with Intel Quartus Prime software 
  • Familiarity with MATLAB and Simulink from MathWorks 
  • Familiarity with digital modem design is helpful, but not necessary

Duration & Attendance

2 days

Target Audience

Hardware engineers who develop and work with DSP algorithms and computationally intense applications for Altera FPGAs that need high performance

Additional Information

Teaching Methods & Tools

1. Course book
2. Lab's handbook and lab files
3. Quartus Prime
4. MATLAB and Simulink 
5. DSP Builder for Altera FPGAs
6. Modelsim

Evaluation & Certification

Each attendee receives an official certificate from Altera and from Arm (Exam must be passed).