Creating PCI Express Links in Intel FPGAs

Course Objectives

This course provides all necessary theoretical and practical know-how to create PCI Express links in Intel FPGAs.
The course goes into great depth and touches upon every aspect of the features and functionality of the Hard IP for PCI Express found in Intel devices.
The course begins with an overview of PCI Express architecture, then teaches how to build Hard IP for PCI Express design, simulate the design, and debug the design.
The course covers PCI Express Gen3 and Gen10 devices as well.
Configuration via protocol (CvP) and Partial Reconfiguration over Protocol (PRoP) design flow are also covered.
The course continues with the parameter editor in Qsys to customize the Hard IP for a specific hardware and how to connect it to Avalon-ST and Avalon-MM cores, using DMA between Hard PCIe and on-chip memory, and design implementation guidelines.
The course ends with introduction of Intel's PCI Express device drivers.
The course combines 60% theory with 40% practical work in every meeting.
The practical labs cover most of the theory and also include practical digital design.

General Information


  • FPGA design
  • VHDL/Verilog
  • ModelSim
  • SignalTap II

Duration & Attendance

2 days

Target Audience

Hardware engineers who develop FPGAs and would like to build a PCI Express design with Intel Hard IP, simulate and debug it.

Additional Information

Teaching Methods & Tools

  • Synthesizer and Place & Route: Quartus Prime 
  • ModelSim 
  • Course book (including labs)
  • Stratix V FPGA development kit
  • PCIe Passive Adaptive kit