Cortex-A76 & Cortex-A55 MPCore Software Development for Agilex 5 SoC

This course is a unique crafted combination of content from Altera, Arm and HandsOn-Training to cover all of the essential know-how, highlighting the Agilex 5 SoC architecture and capabilities as well as the Cortex-A76 and Cortex-A55 MPCore and their configuration options. 
The training is architected for embedded engineers and system designers, bridges the gap between hardware development in Quartus Prime and software implementation in Linux.
You will move from high-level architecture to hands-on bitstream generation, multi-stage booting, and Yocto-based OS builds.
Security and other advanced topics are also covered.
The training has an extensive hands-on lab to experience with the theory topics. 

The training starts by overview the Agilex 5 SoC FPGA architecture with an emphasis on the Hard Processor System (HPS), as well as the configuration and boot schemes with the firts and second bootloaders along with Linux OS. 
The course introduces the ARMv8-A architecture, instruction set, and the new model to handle interrupts and exceptions.

The course continues by covering the Cortex-A76 and Cortex-A55 MPCore architecture based on DynamIQ technology, memory management unit, memory model, cache and branch prediction, cache coherency, processes synchronization, barriers, Generic Interrupt Controller (GIC), debug, and TrustZone, as well as other security features.