Intel FPGA Designer Program with VHDL

This training program provides all necessary theoretical and practical know-how to design Intel FPGA using VHDL standard language and Quartus Prime software tools.
The course intention is to train computer and electronics engineers from scratch to a practical work level.
The course goes into great depth, and touches upon every aspect of the VHDL standard and Intel FPGA design with directly connected to the topics needed in the industry today.
The course combines 50% theory with 50% practical work in every meeting with Terasic DE0-CV evaluation board.
The practical labs cover all the theory and also include practical digital design.
The program provides extra labs/mini projects for homework between meetings.
The first part of the program (5 days) begins with an overview of the current programmable logic devices and their capabilities, continues with an in-depth study of VHDL language with all of its structures, involves writing test-bench programs and employ a simulation tool.
The second part of the program (7 days) starts with an overview of Quartus Prime features, projects types and management, design methodology, and using IP cores from the IP catalog.
Qsys system integration tool, state machine editor, memory editor, Altera SD for OpenCL, and DSP Builder are also introduced in high level.
The course continuous with Quartus Prime compilation flow, incremental compilation concept, working with messages, viewing compilation reports, RTL and technology views, state machine viewer, and how to use the chip planner tool, I/O planning with the pin planner, with the BluePrint Platform Designer, and programming and configuration of FPGA. In addition attendee will learn how to write code for synthesis and employ recommended digital design practices.
The course also teaches the TimeQuest Tool, how insert timing constraints, analyze design timing issues and solve them, and how to debug the design on board use various debugging tools.
The third part of the program (3 days) covers advanced digital design concepts and optimizations.
The training teaches how to design multiple-clock domains with various synchronization techniques, and measure the MTBF of the solution in TimeQuest.
In addition this part teaches how to increase design frequency with pipeline techniques, physical synthesis, fast arithmetic algorithms, and methods to decrease design area with resource & functionality sharing techniques.
At the end of the program engineers will feel confidence to design simple & complex FPGA projects by their own.