Designing with Stratix 10
Course Objectives
Intel Stratix 10 introduces its new architecture, HyperFlex
along with 14nm Intel Tri-Gate technology.
The new architecture allows FPGA designers to control their design performance by using registers throughout the core fabric, which provides a better approach to retiming, pipelining and optimization, in order to achieve timing closure faster.
This course provides all practical know-how needed to achieve higher productivity in Intel Stratix 10 FPGAs.
The course goes deep into the HyperFlex architecture and expose all Quartus Prime Pro features, design new methodologies and new tools such as Fast Forward Compile.
The course provides practical tools and design methods for engineers in order to increase their productivity by finish their projects quicker with best results.
The new architecture allows FPGA designers to control their design performance by using registers throughout the core fabric, which provides a better approach to retiming, pipelining and optimization, in order to achieve timing closure faster.
This course provides all practical know-how needed to achieve higher productivity in Intel Stratix 10 FPGAs.
The course goes deep into the HyperFlex architecture and expose all Quartus Prime Pro features, design new methodologies and new tools such as Fast Forward Compile.
The course provides practical tools and design methods for engineers in order to increase their productivity by finish their projects quicker with best results.
General Information
Prerequisites
- Quartus Prime Pro software
- VHDL/Verilog/SystemVerilog
- TimeQuest
- FPGA design experience
Duration & Attendance
3 days
Target Audience
Digital hardware engineers and FPGA team leaders, who would like to design with Stratix 10 FPGA and achieve higher productivity in their design
Additional Information
Teaching Methods & Tools
- Quartus Prime Pro
- Modelsimr
- Course book (including labs)