Designing with NIOS II Processor using Qsys System Integration Tool

This course will teach you how to quickly build Nios II soft processor designs for Intel FPGAs using Intel's Qsys system-level integration tool.
You will become proficient with Qsys and expand your knowledge of the Quartus Prime FPGA design software. 
Since Qsys makes design reuse easy through standard interfaces, we will examine the Intel Avalon-Memory Mapped and Streaming Interfaces as well as introduce the AMBA AXI interface standard from ARM.
System Console debugging tool is also covered in details.
The course teaches the Nios II architecture and its memory, peripherals, how to manage SoC system, how to configure system based on Nios II, how to transfer data through the Bus system and internal interconnect, how to connect external memories, how to build a system with Qsys, how to handle interrupts, how to develop software and ways for debugging.
The course continuous with a focus on appending custom instruction and custom components to enhance performance, use of simulation models (BFMs), and creating SoC test-benches.
The course then teaches how to access peripherals through the Nios II Hardware Abstraction Layer (HAL), its specific APIs and file system.
The course then describes in details the Nios II BSP features such as HAL system header file, , boot sequence, assessing and reducing code size, and Nios II exceptions.
The second part of the course focuses on practical use of advanced debug features such as JTAG debug core, multi-processor systems, and how to measure code performance with performance counter and profiler.
The course ends with hardware acceleration using custom instructions and custom components, and using Direct Memory Access (DMA).
This course will teach you how to quickly build Nios II soft processor designs for Intel FPGAs using Intel's Qsys system-level integration tool. You will become proficient with Qsys and expand your knowledge of the Quartus Prime FPGA design software. 
Since Qsys makes design reuse easy through standard interfaces, we will examine the Intel Avalon-Memory Mapped and Streaming Interfaces as well as introduce the AMBA AXI interface standard from ARM.
System Console debugging tool is also covered in details.
The course teaches the Nios II architecture and its memory, peripherals, how to manage SoC system, how to configure system based on Nios II, how to transfer data through the Bus system and internal interconnect, how to connect external memories, how to build a system with Qsys, how to handle interrupts, how to develop software and ways for debugging.
The course continuous with a focus on appending custom instruction and custom components to enhance performance, use of simulation models (BFMs), and creating SoC test-benches.
The course then teaches how to access peripherals through the Nios II Hardware Abstraction Layer (HAL), its specific APIs and file system.The course then describes in details the Nios II BSP features such as HAL system header file, boot sequence, assessing and reducing code size, and Nios II exceptions.
The second part of the course focuses on practical use of advanced debug features such as JTAG debug core, multi-processor systems, and how to measure code performance with performance counter and profiler.
The course ends with hardware acceleration using custom instructions and custom components, and using Direct Memory Access (DMA).