Designing for High Productivity & Low Power
Course Objectives
FPGA engineers face many challenges while developing with Intel
Stratix, Arria families and even with Cyclone family with high utilization
(80-90%), such as long compilation time, power consumption, performance variation due to
small/medium changes in the design and resource utilization.
This course provides all practical know-how needed to achieve higher productivity in Intel FPGAs.
The course provides practical tools and design methods for engineers in order to increase their productivity by finish their projects quicker with best results.
This course provides all practical know-how needed to achieve higher productivity in Intel FPGAs.
The course provides practical tools and design methods for engineers in order to increase their productivity by finish their projects quicker with best results.
General Information
Prerequisites
- Quartus Prime software
- VHDL/Verilog
- TimeQuest
- FPGA design experience
Duration & Attendance
2 days
Target Audience
Digital hardware engineers and FPGA team leaders, who would like to enhance their FPGA skills and achieve higher productivity in their FPGA design
Additional Information
Teaching Methods & Tools
- Synthesizer and Place & Route: Quartus Prime
- Course book (including labs)