Verilog for Synthesis

Course Objectives

This course provides all necessary theoretical and practical know?how to write synthesizable HDL code through Verilog standard language.
The course goes into great depth and teaches efficient methods for writing Verilog code in a way that produces the precise digital circuit for various constraints like high frequency, low power, and minimal area.
The course covers the full synthesis process flow starting from reviewing methodologies, using development tools, adding constraints, implementing every Verilog structure in an optimal way, understanding the problems with bad coding style, learning the differences between simulation pre? and post?synthesis, analyzing critical paths, and reading and analyzing synthesis reports.
In addition, the course focuses on writing efficient code to save area, increasing frequency, designing for low power consumption, dealing with skew problems, working with external IPs, using attributes in Verilog code, implementing reliable, and high?speed finite state machines, solving design problems like high fanout and more.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory and also include practical digital design.

General Information


  • FPGA design
  • Verilog

Duration & Attendance

5 days

Target Audience

Hardware engineers who develop FPGAs and would like to enhance their skills, in order to understand synthesis limitations, to acquire better expertise on avoiding digital problems and to be to write efficient coding style for synthesis

Additional Information

Teaching Methods & Tools

  • Simulator: Modelsim
  • Synthesizer and Place & Route: Quartus Prime
  • Course book (including labs)