Verilog Essentials Simulation & Synthesis

Course Objectives

This course provides all necessary theoretical and practical know?how to design programmable logic devices using Verilog standard language.
The course goes into great depth, and touches upon every aspect of the standard with directly connected to the topics needed in the industry today.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory and also include practical digital design.
The course begins with an overview of the current programmable logic devices and their
capabilities, continues with an in?depth study of VHDL language with all of its structures,
involves writing test-bench programs and employ a simulation tool.
The course ends with a synthesis overview and emphasizes the difference between testing code and synthesizable code.

General Information


  • A basic background in digital logic

Duration & Attendance

5 days

Target Audience

Hardware engineers who would like start developing FPGA or CPLD. System engineers who would like to upgrade their professional skills.

Additional Information

Teaching Methods & Tools

  • Simulator: Modelsim
  • Synthesizer and Place & Route: Quartus Prime
  • Terasic Evaluation board DE0?CV
  • Course book (including labs)