VHDL Expert Simulation & Synthesis

Course Objectives

This course expands the theoretical and practical know?how to write synthesizable and advanced test?benches through VHDL standard language.
The course goes into great depth and teaches the advanced features of the VHDL language to design complex projects, sophisticated testbench, full generic design for reuse purposes, and advanced use of functions and procedures.
In addition, the course touches upon high frequency design problems, minimal area design, advanced timing analysis, advanced state machine design, design optimal arithmetic circuits, and much more.
The course emphasizes the most recent updates of the VHDL2008 standard, and guides how to employ them in new designs.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory and also include practical digital design.
This course also enriches digital engineers with many years of experience.

General Information


  • FPGA design
  • VHDL

Duration & Attendance

5 days

Target Audience

Hardware engineers who develop FPGAs and would like to enhance their skills, in order to become experts with VHDL language

Additional Information

Teaching Methods & Tools

  • Simulator: Modelsim
  • Synthesizer and Place & Route: Quartus Prime
  • Course book (including labs)