SystemVerilog Essentials Simulation & Synthesis

Course Objectives

This course provides all necessary theoretical and practical know?how to design programmable logic devices using SystemVerilog standard language.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory and also include practical digital design.
SystemVerilog is a significant new enhancement to Verilog and includes major extensions into abstract design, testbench, formal, and C-based APIs.
SystemVerilog also defines new layers in the Verilog simulation strata.
These extensions provide significant new capabilities to the designer, verification engineer and architect, allowing better teamwork and co?ordination between different project members.
The course goes into great depth, and touches upon every aspect of the standard with directly connected to the topics needed in the industry today.
The course emphasizes the difference between testing code and synthesizable code.

General Information


  • Background in digital logic
  • Verilog language

Duration & Attendance

4 days

Target Audience

Hardware or software e ngineers who would like to design with SystemVerilog. System engineers who would like to enhance their professional skills.

Additional Information

Teaching Methods & Tools

  • Simulator: Modelsim
  • Synthesizer and Place & Route: Quartus Prime
  • Course book (including labs)