Quartus Prime Pro for Vivado Users

Course Objectives

This course provides all theoretical and practical know-how to design programmable devices of Intel with Quartus Prime Pro design software.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory.
The course starts with an overview of the Quartus Prime Pro design software features versus Vivado, Quartus Prime Pro projects types and management, design methodology, and using IP cores from the IP catalog.
Platform Designer, state machine editor, memory editor, Intel SDK for OpenCL, and DSP Builder are also introduced in high level.
The course continues with Quartus Prime Pro compilation flow,working with messages, viewing compilation reports, RTL and technology views, state machine viewer, and how to use the chip planner tool.
The course also touches upon synthesis and Place & Route settings and assignment editor,optimizations, and various advisors.
The course ends with I/O planning with the pin planner, with the Interface Planner, programming and configuration of FPGA/CPLD.

General Information


  • VHDL/Verilog beginners and advanced users who are new to Intel FPGAs

Duration & Attendance

2 days

Target Audience

Hardware engineers who use Xilinx FPGAs with the Vivado software, and would like to be specialized with Intel FPGAs and Quartus Prime software

Additional Information

Teaching Methods & Tools

  • Synthesizer and Place & Route: Quartus Prime Pro
  • Course book (including labs)

Evaluation & Certification

Certification is provided to each attendee