Quartus Prime Foundation

Course Objectives

This course provides all theoretical and practical know-how to design programmable devices of Intel with Quartus Prime design software.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory.
The course starts with an overview of the Quartus Prime design software features, Quartus Prime projects types and management, design methodology, and using IP cores from the IP catalog.
Qsys system integration tool, state machine editor, memory editor, Altera SD for OpenCL, and DSP Builder are also introduced in high level.
The course continues with Quartus Prime compilation flow, incremental compilation concept, working with messages, viewing compilation reports, RTL and technology views, state machine viewer, and how to use the chip planner tool.
The course also touches upon synthesis and Place & Route settings and assignment editor, optimizations, design assistant and various advisors.
The course ends with I/O planning with the pin planner, with the BluePrint Platform Designer, and programming and con figuration of FPGA/CPLD.

General Information


VHDL/Verilog beginners and advanced users who are new to Intel FPGAs.

Duration & Attendance

2 days

Target Audience

Hardware engineers who program with VHDL/Verilog languages and would like to be specialized with Intel FPGAs and Quartus Prime software

Additional Information

Teaching Methods & Tools

  • Synthesizer and Place & Route: Quartus Prime
  • Course book (including labs)

Evaluation & Certification

Certification is provided to each attendee