Partial Reconfiguration with Intel FPGAs

Course Objectives

This course provides all necessary theoretical and practical know-how to use the partial reconfiguration methodology and design flow in order to reprogram one or more parts of a design dynamically, while the rest of the design continues to operate.
The course begins with an overview of what is partial reconfiguration, its main applications, PR definitions for region, partition, persona, PR host and control block.
The course continues with PR hierarchical design flow, design partition recommendations, tools and LogicLock regions. Then timing closure is discussed for PR, changing port values during PR, management of global resources, debugging PR regions.
The course teaches how to design PR host (internal or external), PR host IP for region management, PR controller IP, how to program and configure PR, and PR project full design flow in greater details.
The course combines 50% theory with 50% practical work in every meeting.
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General Information

Prerequisites

  • FPGA design
  • VHDL/Verilog
  • TimeQuest
  • Quartus Prime Pro
  • Avalon
  • ModelSim

Duration & Attendance

2 days

Target Audience

Hardware engineers who develop FPGAs and would like to apply the PR methodology into Arria 10 or Stratix 10 devices.

Additional Information

Teaching Methods & Tools

  • Synthesizer and Place & Route: Quartus Prime Pro
  • Course book (including labs)
  • Intel Stratix 10 GX FPGA Development Kit (optional)