Designing with i.MX8M SoC (3 days)

Course Objectives

Designing with NXP i.MX8M SoC is a 3-days deep-dive training to the latest NXP application processor family. 
The first part of the course starts by overviewing the i.MX8M Family and its Target applications, Device architecture (Quad/Dual/Dual-Lite), and family roadmap (i.MX8/8X). 
The course then overviews various i.MX8M features such as video & graphics capabilities, audio capabilities, Cortex-A53, Cortex-M4, multicore, boot sequence, debug, system bus and interconnect, memory system (L1 cache, L2 cache, OCRAM, ROM, DDR controller), NAND/NOR, SD/eMMC, interrupts, DMA, fuses, pin mux and GPIO. 
The course then introduces the connectivity in i.MX8M such as PCIe, USB, and other general-purpose connectivity (SPI, i2C, UART, PWM, GPT, Ethernet and GPIO).Clock, PLL, power architecture, as well as debug and security are also introduced. 
The second part of the course goes into advanced topics such as multicore configurations (AMP and SMP), the MU (Message Unit) and Sema4 (Semaphore) in order to communicate between Cortex-A53 and Cortex-M4, Interrupts partition strategy, and the boot process in multicore including secure boot.
Power saving techniques are also covered in this section. 
The final part focus on i.MX8M multimedia features, covering the display controller, GPU, and VPU.

Available Countries


General Information


  • Computer architecture background
  • ARM architecture is an advantage but not mandatory
  • Experience in developing embedded systems
  • C/C++ knowledge

Duration & Attendance

3 days

Target Audience

Software engineers that would like developing software and BSP for platforms based on i.MX8M SoC.

Additional Information

Teaching Methods & Tools

  • Board: Variscite´s SoM: VAR-SOM-MX8
  • Course book
  • Labs handbook