Designing with Nios II Processor for Hardware Engineers
Course Objectives
This course provides all theoretical and practical know-how to design Intel FPGAs based on the Nios II soft processor under Quartus Prime software.
The course combines 50% theory and 50% practical work on Terrasic DE series evaluation board.
The course starts with Nios II processor system hardware development, Nios II soft core capabilities, and continues with deep methodic training of the Nios II architecture.
The course teaches the Nios II architecture and its memory, peripherals, how to manage SoC system, how to configure system based on Nios II, how to transfer data through the Bus system and internal interconnect, how to connect external memories, how to build a system with Qsys, how to handle interrupts, how to develop software and ways for debugging.
The second part of the course focuses on appending custom instruction and custom components to enhance performance, use of simulation models (BFMs), and creating SoC test?benches.
The course ends with multi?Nios II systems (multicore) design, the design considerations, and how to debug multiple processors at the same time.
The course combines 50% theory and 50% practical work on Terrasic DE series evaluation board.
The course starts with Nios II processor system hardware development, Nios II soft core capabilities, and continues with deep methodic training of the Nios II architecture.
The course teaches the Nios II architecture and its memory, peripherals, how to manage SoC system, how to configure system based on Nios II, how to transfer data through the Bus system and internal interconnect, how to connect external memories, how to build a system with Qsys, how to handle interrupts, how to develop software and ways for debugging.
The second part of the course focuses on appending custom instruction and custom components to enhance performance, use of simulation models (BFMs), and creating SoC test?benches.
The course ends with multi?Nios II systems (multicore) design, the design considerations, and how to debug multiple processors at the same time.
General Information
Prerequisites
- Quartus Prime software and Qsys
- SignalTap II Embedded Logic Analyzer
- ModelSim
Duration & Attendance
2 days
Target Audience
Hardware and system engineers who would like to design with Intel Nios II soft processor
Additional Information
Teaching Methods & Tools
- Simulator: Modelsim
- Synthesizer and Place & Route: Quartus Prime
- Terrasic Cyclone V GX Evaluation board
- Course book (including labs)
Evaluation & Certification
Certification is provided to each attendee