Designing with DSP Builder for Intel FPGAs

Course Objectives

Learn the timing-driven Simulink® design flow to implement high-speed DSP designs. 
This course focuses on implementing DSP algorithms using the advanced blockset capability of DSP Builder—an interface between Quartus Prime software & MATLAB and Simulink from MathWorks.
You'll analyze & design your DSP algorithm using the DSP Builder advanced blockset in MATLAB & Simulink.
You'll explore architecture & performance tradeoffs with system-level constraints.
Also you'll verify functionality & performance of generated hardware in the Quartus Prime software.
Finally, you'll speed design time by incorporating ready-made ModelIP cores in your design.

General Information


  • Familiarity with DSP fundamentals and design 
  • Familiarity with Intel Quartus Prime software 
  • Familiarity with MATLAB and Simulink from MathWorks 
  • Familiarity with digital modem design is helpful, but not necessary

Duration & Attendance

2 days

Target Audience

Hardware engineers who develop and work with DSP algorithms and computationally intense applications for Altera FPGAs that need high performance

Additional Information

Teaching Methods & Tools

  • Synthesizer and Place & Route: Quartus Prime
  • MATLAB and Simulink version 2017b
  • DSP Builder for Intel FPGAs 
  • Modelsim simulator
  • Course book (including labs)