Building Gigabit Interfaces in Intel 28nm Transceiver Devices

Course Objectives

In this course, you will learn how you can build high-speed, gigabit interfaces using the 28-nm embedded transceivers found in Cyclone V, Arria V and Stratix V FPGA families.
You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols.
You will learn how to optimize and debug both the digital and analog sections of your transceiver design.
You will gain an understanding of the transceiver reconfiguration controller and how you can use it to fine tune transceiver settings and add flexibility to your transceiver design.
Lastly, you will be made aware of common "gotchas” that occur in transceiver designs and what steps you can take to avoid them.

General Information


  • FPGA design
  • Quartus Prime and TimeQuest
  • SignalTap II
Note: familiarity with high-speed interfaces and transmission protocols is helpful, nut not required

Duration & Attendance

2 days

Target Audience

Hardware engineers who develop FPGAs and would like to build gigabit interfaces

Additional Information

Teaching Methods & Tools

  • Synthesizer and Place & Route: Quartus Prime
  • Course book (including labs)
  • Evaluation board (optional)