Introduction to Timing Analysis with TimeQuest
Course Objectives
This course provides all theoretical and
practical know-how start writing sdc files and analyze your design in TimeQuest
tool.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory.
The course starts with an overview of what need to be constrained in every design, the timing terminology used by the tools.
The course continuous by introducing the clock constraints, I/O constraints and exception constraints.
The training explains how to generate and read the various reports in TimeQuest in order to solve timing issues.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory.
The course starts with an overview of what need to be constrained in every design, the timing terminology used by the tools.
The course continuous by introducing the clock constraints, I/O constraints and exception constraints.
The training explains how to generate and read the various reports in TimeQuest in order to solve timing issues.
General Information
Prerequisites
FPGA design
FPGA architecture
Quartus Prime software
FPGA architecture
Quartus Prime software
Duration & Attendance
2 days
Target Audience
Digital hardware engineers who program with VHDL/Verilog languages and would like to constrain and analyze their design timing.
Additional Information
Teaching Methods & Tools
Synthesizer and Place & Route: Quartus Prime Standard
Course book (including labs)
Course book (including labs)