Advanced Verilog for High Productivity

Course Objectives

This course provides all necessary theoretical and practical know-how to write synthesizable Verilog code high productivity in an efficient way.
The course goes into great depth and teaches efficient methods for writing Verilog code in a way that produces the precise digital circuit for various constraints like high frequency, low power, and minimal area.
The course starts by introducing power consumption challenges and how to write efficient Verilog code in order to decrease power in ASIC designs, including resource sharing, functionality sharing, state machine encoding, minimizing transitions on bus, clock gating, how to control counters, retiming and much more.
In addition, the course focuses on writing efficient code to save area, alternative algorithms for arithmetic circuits including counters, adders, multipliers and comparators.
For high frequency design, the training goes into pipeline technique including efficiency, balancing, advantages and disadvantages, skew and high fanout issues.
The course combines 50% theory with 50% practical work in every meeting.
The practical labs cover all the theory and also include practical digital design.

General Information

Prerequisites

  • Verilog
  • Digital Design

Duration & Attendance

3 days

Target Audience

Hardware engineers who develop ASICs and would like to enhance their skills, in order to understand synthesis limitations, write efficient coding style for low power, low area or high frequency.

Additional Information

Teaching Methods & Tools

  • Simulator: Modelsim
  • Synthesizer: Quartus Prime
  • Course book (including labs)